Job Description

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a part of Marvell's Central Physical Design team, you'll work alongside a talented group of engineers responsible for backend design services across Marvell's System-on-Chip (SoC) portfolio. This team supports the physical design needs of multiple SoC design groups and operates at the heart of Marvell's mission to deliver high-performance, low-power, and reliable custom Processor and ASIC solutions for applications in server, optical DSP, and networking. What You Can Expect In this Senior Staff role, you will play a critical role in place and route (PNR) performance and physical verification, bringing Marvell's next-generation high-performance chips to market. With your expertise, you'll tackle complex challenges across place and route, timing closure, and signal integrity, and physical verification, ensuring robust, reliable, and high-speed SoC designs. Your contributions will help Marvell maintain its competitive edge in the data infrastructure sector, and you'll be instrumental in delivering high-quality silicon for Marvell's diverse customer base. Hands-On Physical Design and Verification: Lead physical design tasks, including floorplan, placement, clock tree synthesis and routing. Timing and power optimizations to meet target power-performance metrics. Lead physical verification tasks, including Design Rule Checking (DRC), Layout Versus Schematic (LVS), and antenna checks, ensuring high-quality designs meet foundry requirements. Take ownership of block- and chip-level PNR, from floor planning and clock tree synthesis to routing and timing closure, with a focus on delivering efficient, manufacturable designs. Advanced Design Methodologies: Engage in the development of cutting-edge physical design flows and methodologies, leveraging best practices in backend design to streamline operations and improve design outcomes. Collaborate with frontend, integration, and backend teams to drive successful tapeouts, supporting a robust design process that enables seamless cross-functional teamwork. Process Automation and Efficiency Optimization: Develop scripts and process automation (Makefile, Tcl, Perl) to improve design flow efficiency, streamline repetitive tasks, and ensure consistent, reliable outcomes across projects. Contribute to Marvell's mission by innovating physical design workflows that meet tight schedules without compromising quality. What We're Looking For Education & Experience: Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field. 6+ years of hands-on experience in physical design and verification for advanced CMOS process nodes (e.g., 7nm, 5nm, or below). Technical Expertise: Proven track record of independently handling chip-level P&R and successful tapeouts of complex SoC chips under rigorous deadlines. Proficient with industry-standard EDA tools, including Cadence Genus and Innovus, Synopsys IC Compiler, Fusion Compiler, and verification tools like Calibre. Strong understanding of static timing analysis tools (Tempus, PrimeTime) and power integrity analysis tools (Voltus, PrimeRail). Expertise in extraction (QRC, StarRC) and formal verification (LEC, Formality). Working knowledge in physical verification, LVS and DRC checks. Programming & Automation Skills: Proficiency in scripting with Makefile, Tcl, Perl to automate physical design workflows and improve operational efficiency. Key Attributes: Detail-oriented and self-motivated, with strong teamwork skills and effective communication abilities. Marvell offers the opportunity to work on challenging designs that shape the future of data infrastructure. As a Senior Staff Physical Design Engineer specializing in Physical Verification and PNR, you'll be a part of a supportive, innovative environment where your technical expertise drives meaningful impact on projects across a range of applications. Expected Base Pay Range (USD) 121,840 - 182,500, $ per annum The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

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